1. Field of the Invention
The present invention relates to an ESD protection device and particularly to an ESD protection device eliminating ESD current crowding events, so that a higher ESD level may be achieved under MM ESD testing.
2. Description of the Prior Art
ESD damage has become one of the main reliability concerns facing IC (integrated circuit) products. Particularly, when scaled down to the deep sub-micron regime and the thinner gate oxide, the MOS become more vulnerable to ESD stress. For general industrial specifications, the input and output pins of IC products must sustain HBM (Human-Body-Model) ESD stress of over 2000V and MM (Machine-Model) ESD stress of over 200V. Therefore, ESD protection circuits must be placed around the input and output (I/O) pads of the IC to protect IC against the ESD stress.
ESD protection devices are frequently drawn with large device dimensions and realized by finger-type layout to save total layout area. The layout top views and cross-sectional views of the prior arts to improve the ESD level of ESD protection devices by layout method are shown in FIGS. 1A and 1B. It is formed on a P silicon substrate 11 and includes a STI (shallow trench isolation) 13 enclosing an active region 12, a P guard ring 14 enclosing the STI 13, two gates 15, each composed of polysilicon layer 151, gate oxide 152 and spacers 153, and N drain and source region 161 and 162 placed in between and on the outer sides of the gates 15. The gates, source region, and body are typically connected to the ground while the drain region is connected to the input/output pad. The fundamental theorem of ESD protection design is based on the mechanisms of the MOS and the parasitic lateral n-p-n bipolar (BJT) under high current, and high field conduction. FIGS. 2A and 2B are sectional views and an equivalent circuit of a NMOS transistor, with the drain 22 as the collector, substrate 21 as the body and source 23 as the emitter. During ESD stress, high field at the drain causes the N+ to P substrate junction to enter an avalanche breakdown condition, generating excessive electron-hole pairs. The current of the electron-hole pairs forward biases the substrate-source (PN junction), and the voltage drop across the substrate resistances increase the BE junction voltage of the parasitic BJT which is triggered to generate the snapback region in its I-V curves, as shown in FIG. 3. Thus, the parasitic BJT turns on to and bypass the ESD current.
FIGS. 4A and 4B are top and sectional views of another conventional ESD protection device, a gate grounded NMOS. With comparison to the ESD protection device in FIGS. 1A and 1B, it is noted that the bulk substrate resistance of the BB′ region is much larger than that of the AA′ region. This allows the parasitic BJT of the BB′ region to turn on faster than that of the AA′ region with higher collector current to bypass the ESD current and spread through the BB′ region. The parasitic BJT of the BB′ region can provide larger effective area than the AA′ region to discharge the ESD current, therefore it may have a high HBM ESD robustness. However, under MM ESD zapping, the drain node conductivity with higher peak currents of 3˜4 Amps (for 200V MM ESD stress) often cause ESD damage at the corner or finger's end regions. The cause of damage is MM ESD current 3 or 4 times higher through an extremely small resistance than the HBM ESD current. Although the resistance of the AA′ region is smaller than that of the BB′ region, the breakdown current (due to ESD zapping at the drain) of the drain to substrate junction at the AA′ region is still high enough to forward bias and to turn on the parasitic BJT at the AA′ region, before turning on the parasitic BJT at the BB′ region. Thus, an excess of current crowds around the AA′ region and causes device failure at this region. Such damage is commonly shown in photographic training materials used in ESD protection design training courses.